View HYS64D32020GU-8-A_5273758.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

never stop thinking. hys[64/72]d16000gu-[7/8]-a hys[64/72]d32020gu-[7/8]-a unbuffered ddr sdram-modules ddr sdram data sheet, rev. 1.03, jan. 2004 memory products
edition 2004-01 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys[64/72]d16000gu-[7/8]-a hys[64/72]d32020gu-[7/8]-a unbuffered ddr sdram-modules ddr sdram data sheet, rev. 1.03, jan. 2004 memory products
template: mp_a4_v2.2_2003-10-07.fm hys[64/72]d16000gu-[7/8]-a, hys[64/72]d32020gu-[7/8]-a revision history: rev. 1.03 2004-01 previous version: rev. 1.02 2003-11 page subjects (major changes since last revision) all editorial changes we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules table of contents page data sheet 5 rev. 1.03, 2004-01 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 current specification and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules overview data sheet 6 rev. 1.03, 2004-01 10292003-wld7-ij5z 1 overview 1.1 features ? 184-pin unbuffered 8-byte dual-in-line ddr sdram no n-parity and ecc-modules for pc and server main memory applications one rank 16m x 64, 16m x 72 and two rank 32m x 64, 32m 72 organization jedec standard double data rate synchronous drams (ddr sdram) single + 2.5 v ( 0.2 v) power supply built with 128 mb ddr sdrams organised as 16mb x 8 in 66-lead tsopii package programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible serial presence detect with e 2 prom jedec standard mo-206 form factor: 133.35 mm 31.75 mm 4.00 mm max. jedec standard reference layout gold plated contacts table 1 performance -8/-7 1.2 description the hys64/72d16000gu and hys64/72d32020gu are industry standard 184-pin 8-byte dual in-line memory modules (dimms) organized as 16m x 64 and 32m 64 for non-parity and 16m x 72 and 32m x 72 for ecc main memory applications. the memory array is designed with 128mbit double data rate synchronous drams. a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. part number speed code ?7 ? 8unit speed grade component ddr266a ddr200 ? module pc2100-2033 pc1600-2022 ? max. clock frequency @cl2.5 f ck2.5 143 125 mhz @cl2 f ck2 133 100 mhz
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules overview data sheet 7 rev. 1.03, 2004-01 10292003-wld7-ij5z note: all part numbers end with a place code, designating the silicon-die revision. reference information available on request. example: hys 72d32020gu-8-a, indicating rev.a dies are used for the sdram components. the compliance code is printed on the module labels and describes the speed sort fe. ?pc2100?, the latencies (f.e. ?20330? means cas latency = 2, trcd latency = 3 and trp latency =3 ) and the raw card used for this module. table 2 ordering information type compliance code description sdram technology pc2100 (cl=2): hys64d16000gu-7-a pc2100-20330-a1 one rank 128 mb dimm 128 mbit (x8) hys72d16000gu-7-a pc2100-20330-a1 one rank 128 mb ecc-dimm 128 mbit (x8) hys64d32020gu-7-a pc2100-20330-b1 two ranks 256 mb dimm 128 mbit (x8) hys72d32020gu-7-a pc2100-20330-b1 two ranks 256 mb ecc-dimm 128 mbit (x8) pc1600 (cl=2): hys64d16000gu-8-a pc1600-20220-a1 one rank 128 mb dimm 128 mbit (x8) hys72d16000gu-8-a pc1600-20220-a1 one rank 128 mb ecc-dimm 128 mbit (x8) HYS64D32020GU-8-A pc1600-20220-b1 two ranks 256 mb dimm 128 mbit (x8) hys72d32020gu-8-a pc1600-20220-b1 two ranks 256 mb ecc-dimm 128 mbit (x8)
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules pin configuration data sheet 8 rev. 1.03, 2004-01 10292003-wld7-ij5z 2 pin configuration note: s1 and cke1 are used on two rank modules only table 3 pin definitions and functions symbol type 1) 1) i: input; o: output; i/o: bidirectional in-/output; ai: analog input; pwr: power supply; gnd: signal ground; nc: not connected function a0 - a12 i address inputs ba0, ba1 i bank selects dq0 - dq63 i/o data input/output cb0 - cb7 i/o check bits ( 72 organization only) ras, cas , we i command inputs cke0 - cke1 i clock enable dqs0 - dqs8 i/o sdram low data strobes ck0 - ck2, i sdram clock (positive lines) ck0 - ck2 i sdram clock (negative lines) dm0 - dm8 dqs9 - dqs17 i i/o sdram low data mask/ high data strobes s0 , s1 i chip selects for rank0 and rank1 v dd pwr power (+2.5 v) v ss gnd ground v ddq pwr i/o driver power supply v ddid pwr vdd indentification flag v ref ai i/o reference supply v ddspd pwr serial eeprom power supply scl i serial bus clock sda i/o serial bus data line sa0 - sa2 i slave address select nc nc not connected
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules pin configuration data sheet 9 rev. 1.03, 2004-01 10292003-wld7-ij5z table 4 pin configuration frontside backside pin# symbol pin# symbol pin# symbol pin# symbol 1 v ref 48 a0 93 v ss 140 nc / dm8/dqs17 2 dq0 49 nc / cb2 94 dq4 141 a10 3 v ss 50 v ss 95 dq5 142 nc / cb6 4 dq1 51 nc / cb3 96 v ddqd 143 v ddqd 5 dqs0 52 ba1 97 dm0/dqs9 144 nc / cb7 6dq2 key 98 dq6 key 7 v dd 99 dq7 8 dq3 53 dq32 100 v ss 145 v ss 9nc 54 v ddq 101 nc 146 dq36 10 nc 55 dq33 102 nc 147 dq37 11 v ss 56 dqs4 103 nc 148 v dd 12 dq8 57 dq34 104 v ddq 149 dm4/dqs13 13 dq9 58 v ss 105 dq12 150 dq38 14 dqs1 59 ba0 106 dq13 151 dq39 15 v ddq 60 dq35 107 dm1/dqs10 152 v ss 16 ck1 61 dq40 108 v dd 153 dq44 17 ck1 62 v ddq 109 dq14 154 ras 18 v ss 63 we 110 dq15 155 dq45 19 dq10 64 dq41 111 cke1 156 v ddq 20 dq11 65 cas 112 v ddq 157 s0 21 cke0 66 v ss 113 nc (ba2) 158 s1 22 v ddq 67 dqs5 114 dq20 159 dm5/dqs14 23 dq16 68 dq42 115 nc / a12 160 v ss 24 dq17 69 dq43 116 v ss 161 dq46 25 dqs2 70 v dd 117 dq21 162 dq47 26 v ss 71 nc 118 a11 163 nc 27 a9 72 dq48 119 dm2/dqs11 164 v ddq 28 dq18 73 dq49 120 v dd 165 dq52 29 a7 74 v ss 121 dq22 166 dq53 30 v ddq 75 ck2 122 a8 167 nc (a13) 31 dq19 76 ck2 123 dq23 168 v dd 32 a5 77 v ddq 124 v ss 169 dm6/dqs15 33 dq24 78 dqs6 125 a6 170 dq54 34 v ss 79 dq50 126 dq28 171 dq55 35 dq25 80 dq51 127 dq29 172 v ddq 36 dqs3 81 v ss 128 v ddq 173 nc 37 a4 82 v ddid 129 dm3/dqs12 174 dq60 38 v dd 83 dq56 130 a3 175 dq61 39 dq26 84 dq57 131 dq30 176 v ss
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules pin configuration data sheet 10 rev. 1.03, 2004-01 10292003-wld7-ij5z note: pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are nc (?not connected?) on 64 organised non-ecc modules. note: pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are nc (?no-connects?) on x64 organised non-ecc modules. a12 is used for 256 mbit based modules only. 40 dq27 85 v dd 132 v ss 177 dm7/dqs16 41 a2 86 dqs7 133 dq31 178 dq62 42 v ss 87 dq58 134 nc / cb4 179 dq63 43 a1 88 dq59 135 nc / cb5 180 v ddq 44 nc / cb0 89 v ss 136 v ddq 181 sa0 45 nc / cb1 90 nc 137 ck0 182 sa1 46 v dd 91 sda 138 ck0 183 sa2 47 nc / dqs8 92 scl 139 v ss 184 v ddspd table 5 address format density organization memory banks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 128 mb 16m 64 1 16m 8 8 12/2/10 4k 64 ms 15.6 s 128 mb 16m 72 1 16m 8 9 12/2/10 4k 64 ms 15.6 s 256 mb 32m 64 2 16m 8 16 12/2/10 4k 64 ms 15.6 s 256 mb 32m 72 2 16m 8 18 12/2/10 4k 64 ms 15.6 s table 4 pin configuration (cont?d) frontside backside pin# symbol pin# symbol pin# symbol pin# symbol
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules pin configuration data sheet 11 rev. 1.03, 2004-01 10292003-wld7-ij5z figure 1 block diagram: one rank 16m 64 ddr sdram dimm module hys64d16000gu using 8 organized sdrams dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 d0 dm0/dqs9 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d7 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d7 s 0 s s s s s s s s ba0 - ba1 ba0-ba1: sdrams d0 - d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 scl dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 2 sdrams 3 sdrams 3 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5% 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. bax, ax, ras , cas , we resistors: 5.1 ohms + 5% v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 v ref v ddid strap: see note 4 wp spd v dd spd dq4 i/o 3 i/o 4
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules pin configuration data sheet 12 rev. 1.03, 2004-01 10292003-wld7-ij5z figure 2 block diagram: two rank 32m 64 ddr sdram dimm modules hys64d32020gu using 8 organized sdrams dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 dm d8 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 dm d9 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 dm d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 dm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 dm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 dm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 dm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 dm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - an a0-an: sdrams d0 - d15 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d15 s 0 s 1 s s s s s s s s s s s s s s s s cke1 cke: sdrams d8 - d15 ba0 - ba1 ba0-ba1: sdrams d0 - d15 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 i/o 7 dqs dqs dqs dqs dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 4 sdrams 6 sdrams 6 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 v ref v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq 5. bax, ax, ras , cas , we resistors: 3 ohms + 5% scl wp spd v dd spd
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules pin configuration data sheet 13 rev. 1.03, 2004-01 10292003-wld7-ij5z figure 3 block diagram: one rank 16m 72 ddr sdram dimm module hys72d16000gu using 8 organized sdrams dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7 a0 - a13 a0-a13: sdrams d0 - d8 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d8 cas cas : sdrams d0 - d8 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d8 s 0 s s s s s s s s ba0 - ba1 ba0-ba1: sdrams d0 - d8 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 0 i/o 1 i/o 2 i/o 3 d8 i/o 4 i/o 5 i/o 6 i/o 7 s dqs8 dm8 dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 3 sdrams 3 sdrams 3 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v ref v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. bax, ax, ras , cas , we resistors: 5.1 ohm + 5% scl wp spd v dd spd
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules pin configuration data sheet 14 rev. 1.03, 2004-01 10292003-wld7-ij5z figure 4 block diagram: two rank 32m 72 ddr sdram dimm modules hys72d32020gu using 8 organized sdrams dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 dm d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 dm d10 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 dm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 dm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 dm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 dm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 dm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 dm d16 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d17 ras ras : sdrams d0 - d17 cas cas : sdrams d0 - d17 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d17 s 0 s 1 s s s s s s s s s s s s s s s s * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 6 sdrams 6 sdrams 6 sdrams cke1 cke: sdrams d9 - d17 * wire per clock loading ba0 - ba1 ba0-ba1: sdrams d0 - d17 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 0 i/o 1 i/o 2 i/o 3 d8 dm d17 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s s dqs8 dm8/dqs17 dqs dqs table/wiring diagrams dqs dqs dqs dqs dqs dqs dqs dqs dqs v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref *ck2/ck2 v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq 5. bax, ax, ras , cas , we resistors: 3 ohms + 5% a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp spd v dd spd
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules pin configuration data sheet 15 rev. 1.03, 2004-01 10292003-wld7-ij5z figure 5 clock net wiring 4 dram loads dimm ck ck dr am 1 dram2 dr am4 dr am5 dr am6 dr am 1 cap. dr am3 dr am5 cap. cap. dr am 1 cap. dr am5 cap. cap. cap. dr am 1 dr am5 cap. cap. dram3 dram2 dram6 connector connector dimm r = 120 r = 120 connector dimm connector dimm r = 120 r = 120 6 dram loads 3 dram loads 2 dram loads
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules electrical characteristics data sheet 16 rev. 1.02, 2003-11 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 6 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1?w? short circuit output current i out ?50?ma?
data sheet 17 rev. 1.02, 2003-11 hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules electrical characteristics table 7 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) 1) 0 c t a 70 c min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v output supply voltage v ddq 2.3 2.5 2.7 v 2) 2) under all conditions, v ddq must be less than or equal to v dd . eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 3) 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 7) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 7) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 7) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 7)5) 5) v id is the magnitude of the difference between the input level on ck and the input level on ck . vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 6) 6) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 7)8) 7) inputs are not recognized as valid until v ref stabilizes. 8) values are shown per component output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 7) output high current, normal strength driver i oh ??16.2ma v out = 1.95 v 7) output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 7)
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules electrical characteristics data sheet 18 rev. 1.02, 2003-11 3.2 current specification and conditions table 8 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; power-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
data sheet 19 rev. 1.02, 2003-11 hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules electrical characteristics table 9 i dd specification and conditions -8/-7 part number & organization hys64d16000gu-8-a hys64d16000gu-7-a hys72d16000gu-8-a hys72d16000gu-8-a HYS64D32020GU-8-A hys64d32020gu-7-a hys72d32020gu-8-a hys72d32020gu-7-a unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition for maximum values: v dd =2.7v, t a =10c 128mb 128mb 256mb 256mb 64 72 64 72 1 rank 1 rank 2 ranks 2 ranks -8 -7 -8 -7 -8 -7 -8 -7 symbol max max max max i dd0 680 720 765 810 960 1080 1080 1215 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 800 880 900 990 1080 1240 1215 1395 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 36 40 40.5 45 72 80 81 90 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 280 360 315 405 560 720 630 810 ma 5) i dd2q 280 360 315 405 560 720 630 810 ma 5) i dd3p 120 120 135 135 240 240 270 270 ma 5) i dd3n 280 360 315 405 560 720 630 810 ma 5) i dd4r 720 880 810 990 1000 1240 1125 1395 ma 3)4) i dd4w 760 880 855 990 1040 1240 1170 1395 ma 3) i dd5 1440 1520 1620 1710 1720 1880 1935 2115 ma 3) i dd6 20 20 22.5 22.5 40 40 45 45 ma 5) i dd7 2160 2240 2430 2520 2440 2600 2745 2925 ma 3)4)
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules electrical characteristics data sheet 20 rev. 1.02, 2003-11 3.3 ac characteristics table 10 ac timing - absolute specifications ?8/?7 parameter symbol ?8 ?7 unit note/ test condition 1) ddr200 ddr266a min. max. min. max. dq output access time from ck/ck t ac ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck2.5 8 12 7 12 ns cl = 2.5 2)3)4)5) t ck2 10 12 7.5 12 ns cl = 2.0 2)3)4)5) t ck1.5 10 12 ? ? ns cl = 1.5 2)3)4)5) dq and dm input hold time t dh 0.6 ? 0.5 ? ns 2)3)4)5) dq and dm input setup time t ds 0.6 ? 0.5 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.5 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 2.0 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.6 ? +0.5 ns 2)3)4)5) data hold skew factor t qhs ? 1.0 ? 0.75 ns 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2? 2 ? t ck 2)3)4)5) write preamble setup time t wpres 0? 0 ? ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 1.1 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.1 ? 1.0 ? ns slow slew rate 3)4)5)6)10)
data sheet 21 rev. 1.02, 2003-11 hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules electrical characteristics address and control input hold time t ih 1.1 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.1 ? 1.0 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck cl > 1.5 2)3)4)5) t rpre1.5 0.9 1.1 na t ck cl = 1.5 2)3)4)5)11) read preamble setup time t rpres 1.5 ? na ns 2)3)4)5)12) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 50 120e+3 45 120e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 70 ? 65 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 80 ? 75 ? ns 2)3)4)5) active to read or write delay t rcd 20 ? 20 ? ns 2)3)4)5) precharge command period t rp 20 ? 20 ? ns 2)3)4)5) active to autoprecharge delay t rap 20 ? 20 ? ns 2)3)4)5) active bank a to active bank b command t rrd 15 ? 15 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)13) internal write to read command delay t wtr 1? 1 ? t ck cl > 1.5 2)3)4)5) t wtr1.5 2? ? ? t ck cl = 1.5 2)3)4)5) exit self-refresh to non-read command t xsnr 80 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)14) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v 2) input slew rate 1 v/ns for ddr266, and = 1 v/ns for ddr200 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. table 10 ac timing - absolute specifications ?8/?7 parameter symbol ?8 ?7 unit note/ test condition 1) ddr200 ddr266a min. max. min. max.
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules electrical characteristics data sheet 22 rev. 1.02, 2003-11 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v oh(ac) and v ol(ac) . 11) cas latency 1.5 operation is supported on ddr200 devices only 12) t rpres is defined for cl = 1.5 operation only 13) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 14) a maximum of eight autorefresh commands can be posted to any given ddr sdram device.
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules spd contents data sheet 23 rev. 1.03, 2004-01 10292003-wld7-ij5z 4 spd contents table 11 spd codes for pc1600 modules -8 byte# description 128mb x64 1rank ?8 128mb x72 1rank ?8 128mb x64 2ranks ?8 128mb x64 2ranks ?8 hex. hex. hex. hex. 0 number of spd bytes 128 80 80 80 80 1 total bytes in serial pd 256 08 08 08 08 2 memory type ddr-sdram 07 07 07 07 3 number of row addresses 12 0c 0c 0c 0c 4 number of column addresses 10 0a 0a 0a 0a 5 number of dimm banks 1/2 01 01 02 02 6 module data width 64/ 72 40 48 40 48 7 module data width (cont?d) 0 00 00 00 00 8 module interface levels sstl_2.5 04 04 04 04 9 sdram cycle time at cl = 2.5 8ns 80 80 80 80 10 access time from clock at cl = 2.5 0.8 ns 80 80 80 80 11 dimm config non-ecc/ecc 00 02 00 02 12 refresh rate/type self-refresh 15.6 ms 80 80 80 80 13 sdram width, primary 808080808 14 error checking sdram data witdh na/ 800080008 15 minimum clock delay for back-to-back random column address t ccd =1 clk 01 01 01 01 16 burst length supported 2, 4 & 8 0e 0e 0e 0e 17 number of sdram banks 4 04 04 04 04 18 supported cas latencies cas latency = 2 & 2.5 0c 0c 0c 0c 19 cs latencies cs latency = 0 01 01 01 01 20 we latencies write latency = 1 02 02 02 02 21 sdram dimm module attributes unbuffered 20 20 20 20 22 sdram device attributes: general ?c0c0c0c0 23 min. clock cycle time at cas latency = 2 10 ns a0 a0 a0 a0 24 access time from clock for cl = 2 0.8 ns 80 80 80 80 25 minimum clock cycle time for cl = 1.5 not supported 00 00 00 00
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules spd contents data sheet 24 rev. 1.03, 2004-01 10292003-wld7-ij5z 26 access time from clock at cl = 1.5 not supported 00 00 00 00 27 minimum row precharge time 20 ns 50 50 50 50 28 minimum row act. to row act. delay t rrd 15 ns 3c 3c 3c 3c 29 minimum ras to cas delay t rcd 20 ns 50 50 50 50 30 minimum ras pulse width t ras 50 ns 32 32 32 32 31 module bank density (per bank) 128 mbyte 20 20 20 20 32 addr. and command setup time 1.1 ns b0 b0 b0 b0 33 addr. and command hold time 1.1 ns b0 b0 b0 b0 34 data input setup time 0.6 ns 60 60 60 60 35 data input hold time 0.6 ns 60 60 60 60 36 to 40 superset information ? 41 minimum core cycle time t rc 70 ns 46 46 46 46 42 min. auto refresh cmd cycle time t frc 80 ns 50 50 50 50 43 maximum clock cycle time t ck 12 ns 30 30 30 30 44 max. dqs-dq skew tdqsq 0.6 ns 3c 3c 3c 3c 45 x-factor tqhs 1.0 ns a0 a0 a0 a0 46 to 61 superset information ? 00 00 00 00 62 spd revision revision 0.0 00 00 00 00 63 checksum for bytes 0 - 62 ? 84 96 85 97 64 manufactures jedec id codes ? 65 to 71 manufactures ? infineon infineon infineon infineon 72 module assembly location ? ? ? ? ? 73 to 90 module part number ? ? ? ? ? 91 to 92 module revision code ? ? ? ? ? 93 to 94 module manufacturing date ? ? ? ? ? 95 to 98 module serial number ? ? ? ? ? 99 to 127 ? ? ? ? ? ? 128 to 255 open for customer use ? ? ? ? ? table 11 spd codes for pc1600 modules -8 (cont?d) byte# description 128mb x64 1rank ?8 128mb x72 1rank ?8 128mb x64 2ranks ?8 128mb x64 2ranks ?8 hex. hex. hex. hex.
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules spd contents data sheet 25 rev. 1.03, 2004-01 10292003-wld7-ij5z table 12 spd codes for pc2100 modules -7 byte# description 128mb x64 1rank ?7 128mb x72 1rank ?7 128mb x64 2ranks ?7 128mb x64 2ranks ?7 hex. hex. hex. hex. 0 number of spd bytes 128 80 80 80 80 1 total bytes in serial pd 256 08 08 08 08 2 memory type ddr-sdram 07 07 07 07 3 number of row addresses 12 0c 0c 0c 0c 4 number of column addresses 10 0a 0a 0a 0a 5 number of dimm banks 1/2 01 01 02 02 6 module data width 64/ 72 40 48 40 48 7 module data width (cont?d) 0 00 00 00 00 8 module interface levels sstl_2.5 04 04 04 04 9 sdram cycle time at cl = 2.5 7ns 70 70 70 70 10 access time from clock at cl = 2.5 0.75 ns 75 75 75 75 11 dimm config non-ecc/ecc 00 02 00 02 12 refresh rate/type self-refresh 15.6 ms 80 80 80 80 13 sdram width, primary 808080808 14 error checking sdram data witdh na/ 800080008 15 minimum clock delay for back-to-back random column address t ccd =1 clk 01 01 01 01 16 burst length supported 2, 4 & 8 0e 0e 0e 0e 17 number of sdram banks 4 04 04 04 04 18 supported cas latencies cas latency = 2 & 2.5 0c 0c 0c 0c 19 cs latencies cs latency = 0 01 01 01 01 20 we latencies write latency = 1 02 02 02 02 21 sdram dimm module attributes unbuffered 20 20 20 20 22 sdram device attributes: general ?c0c0c0c0 23 min. clock cycle time at cas latency = 2 7.5 ns 75 75 75 75 24 access time from clock for cl = 2 0.75 ns 75 75 75 75 25 minimum clock cycle time for cl = 1.5 not supported 00 00 00 00 26 access time from clock at cl = 1.5 not supported 00 00 00 00
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules spd contents data sheet 26 rev. 1.03, 2004-01 10292003-wld7-ij5z 27 minimum row precharge time 20 ns 50 50 50 50 28 minimum row act. to row act. delay t rrd 15 ns 3c 3c 3c 3c 29 minimum ras to cas delay t rcd 20 ns 50 50 50 50 30 minimum ras pulse width t ras 45 ns 2d 2d 2d 2d 31 module bank density (per bank) 128 mbyte 20 20 20 20 32 addr. and command setup time 0.9 ns 90 90 90 90 33 addr. and command hold time 0.9 ns 90 90 90 90 34 data input setup time 0.5 ns 50 50 50 50 35 data input hold time 0.5 ns 50 50 50 50 36 to 40 superset information ? 41 minimum core cycle time t rc 65 ns 41 41 41 41 42 min. auto refresh cmd cycle time t frc 75 ns 4b 4b 4b 4b 43 maximum clock cycle time t ck 12 ns 30 30 30 30 44 max. dqs-dq skew tdqsq 0.5 ns 32 32 32 32 45 x-factor tqhs 0.75 ns 75 75 75 75 46 to 61 superset information ? 00 00 00 00 62 spd revision revision 0.0 00 00 00 00 63 checksum for bytes 0 - 62 ? 8f 8f 8f 8f 64 manufactures jedec id codes ?c1c1c1c1 65 to 71 manufactures ? infineon infineon infineon infineon 72 module assembly location ? ? ? ? ? 73 to 90 module part number ? ? ? ? ? 91 to 92 module revision code ? ? ? ? ? 93 to 94 module manufacturing date ? ? ? ? ? 95 to 98 module serial number ? ? ? ? ? 99 to 127 ? ? ? ? ? ? 128 to 255 open for customer use ? ? ? ? ? table 12 spd codes for pc2100 modules -7 (cont?d) byte# description 128mb x64 1rank ?7 128mb x72 1rank ?7 128mb x64 2ranks ?7 128mb x64 2ranks ?7 hex. hex. hex. hex.
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules package outlines data sheet 27 rev. 1.03, 2004-01 10292003-wld7-ij5z 5 package outlines figure 6 ddr-sdram dimm module package 93 184 1 133.35 92 6.62 2.36 0.1 ?0.1 b a c 2.175 6.35 64.77 49.53 95 x 1.27 = 120.65 128.95 0.15 ac b a 0.13 31.75 0.1 4 0.1 ac b 0.1 a b c 0.1 1.8 3 min. 10 17.8 0.1 1.27 0.4 4 max. c detail of contacts 0.2 0.05 1 0.2 2.5 1.27 0.1 ac b 0.13 3.8 b 1) 1) 1) on ecc modules only burr max. 0.4 allowed
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules package outlines data sheet 28 rev. 1.03, 2004-01 10292003-wld7-ij5z figure 7 package outlines -raw card a1 (one rank modules) a 4 a 0.1 0.1 b c 128.95 133.35 0.15 b a c b 0.13 31.75 1.27 0.1 c 2.7 max. 0.4 6.35 120.65 2.36 1 64.77 ?0.1 0.1 b a c 1.27 95 x = 6.62 2.175 49.53 92 1.8 0.1 0.1 abc 93 184 17.8 10 0.13 3.8 3 min. 1.27 1 0.05 a 0.1 b c detail of contacts 0.2 2.5 0.2 1) burr max. 0.4 allowed 1) on ecc modules only
hys[64/72]d[16000/32020]gu-[7/8]-a unbuffered ddr sdram-modules package outlines data sheet 29 rev. 1.03, 2004-01 10292003-wld7-ij5z figure 8 package outlines - raw card b1 (two rank modules) ddr-sdram dimm module package two banks modules l-dim-184- 9d 144 145 184 17.80 3 *) on ecc modules only 10.0 3 detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 31.75 pin 1 + 0.13 - + 0.15 - 6.62 49.53 4.0 1.27 4.0 max. + 0.1 - pin 93 2.5d front view backside view detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r *) *)
published by infineon technologies ag http://www.infineon.com

▲Up To Search▲

Price & Availability of HYS64D32020GU-8-A

	To Download HYS64D32020GU-8-A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .